tag:blogger.com,1999:blog-4005332798761431962024-03-13T08:31:04.951-07:00VLSI Design EngineerVLSI Design / ASIC Design / Process
Technology / Test / Silicon Qualification.Prakash Patilhttp://www.blogger.com/profile/16951218341664680207noreply@blogger.comBlogger2125tag:blogger.com,1999:blog-400533279876143196.post-44629299961761036662006-09-01T06:09:00.001-07:002006-09-01T06:17:02.101-07:00ASIC Design EngineerPrakash Patilhttp://www.blogger.com/profile/16951218341664680207noreply@blogger.com0tag:blogger.com,1999:blog-400533279876143196.post-40132478776560997552006-08-19T16:06:00.000-07:002006-08-19T16:27:21.470-07:00VLSI Design Engineer<div style="text-align: center;"> <span style="font-size:130%;">Curriculum Vitae </span><br /></div><div style="text-align: center;"> ================<br /></div><br /><span style="font-weight: bold;font-size:130%;" ><span style="font-family: times new roman;">Prakash Patil </span> </span> <br /><span style="color: rgb(255, 204, 102);">E-mail </span><br /><span style="font-style: italic; color: rgb(51, 102, 255);">PraPatil@gmail.com </span><br /><span style="font-style: italic; color: rgb(51, 102, 255);">PraPatil2k@yahoo.com </span><br /><span style="color: rgb(102, 51, 255);">Prakash.Patil.VLSI@Gmail.com</span><br /><span style="color: rgb(102, 0, 204);">Semiconductor.Career@gmail.com </span><br /><span style="color: rgb(153, 153, 255);">http://www.freewebs.com/prakashpatil </span><br /><br />==========================================================================<br /><br /><span style="font-weight: bold;font-size:130%;" >Objective: </span><br />==========<br />To seek a challenging position in the field of VLSI / ASIC Design / Process<br />Technology / Test.<br /><br /><span style="font-weight: bold;">EXPERIENCE SUMMARY: </span><br />===================<br />One & half years of experience in physical design of Integrated Circuit<br />(IC) on 0.13 micron & 0.18 micron process. Good skills and experience of<br />deep sub micron IO pad library design, verification, and design of test<br />chip, ESD & LATCH-UP issues, and Failure analysis. Programming / Scripting<br />in SKILL, Perl, TCL, C. Good communication skills. Excellent leadership<br />qualities.<br /><br /><span style="font-weight: bold;font-size:130%;" >SKILLS OFFERED: </span><br />===============<br />ASIC / VLSI Physical Design, Process Technology, Test. Expert Currently<br />used 2 years.<br />Software Proficiency: Cadence Tool, Mentor Graphics calibre tool, Hspice /<br />Characterization techniques, ability to develop well-structured and<br />maintainable software tools.<br />Programming / scripting languages like SKILL, Perl and TCL, C, C++ etc.<br />O.S. platform: HP UNIX, Win NT, and LINUX.<br /><br /><span style="font-weight: bold;font-size:130%;" >Professional experience: </span><br />========================<br />3/2001 to 8/2002 Philips Semiconductors, The Netherlands. <br />Standard Cell Design Engineer.<br /> Major role in Shrink CMOS18 micron & CMOS12 micron IO pad library<br />Design. Computer aided physical design of CMOS12 micron library design,<br />verification. Verification & merging of new cells to Standard cell library<br />& maintenance.<br /> SHRINK CMOS18 library physical design, verification: Verification of new<br />cells, merging of new cells & maintenance of complete SHRINK CMOS18 IO pad<br />library. Complete SHRINK CMOS18 micron IO pad library converted from CMOS<br />18 IO pad library. All the IO pad layouts of SHRINK 18 micron standard cell<br />library converted from cmos18 library for SHRINK process. It itself is a<br />big project. <br /> New Physical design Layout like level shifter, PCI, P1394, USB, PECL,<br />SSTL etc.<br /> A role in the silicon qualification (electrical, ESD and Latch-up<br />issues) of the I/O libraries. <br /> Design of test chips for IO pads of standard cell library and<br />participation in the testing and failure analysis. <br /> Besides the general-purpose input, output and bi-directional cells, the<br />current libraries contain new cells developed according industrial<br />standards (SSTL-2, PCI, USB, PECL, etc.).<br /> Well Versed with Physical Design aspects-Floor Planning, P & R, Clock<br />tree synthesis, links to DRC, LVS, etc. Familiarity with Mentor & Cadence<br />tools, Working knowledge of scripting languages like SKILL, PERL and TCL.<br />Ability to lead a team of engineers.<br /><br /> Software used: Cadence complete Backend Qualified Design flow (QDF<br />3.1), Skill scripts, and Calibre Mentor Graphics tool. <br /> O.S. platform used: WinNT, HP-Unix. <br /> Team Size: 4.<br /><br /> Training Undergone: Cadence Qualified Design flow (QDF 3.1): Three &<br />half day of extensive training on complete front end & backend design flow.<br />SKILL language: SKILL language for Cadence design tool. Extensive five days<br />of training.<br /><br /><span style="font-weight: bold;font-size:130%;" >Education:</span><span style="font-weight: bold;"> </span><br />==========<br />1998 - 03/2000 Indian Institute Of Technology Bombay, Mumbai, India<br />Master of Technology in Microelectronics with GPA 6.85 out of 10. <br />Some of the courses studied at M.Tech. are as: <br />VLSI Design, <br />VLSI Technology, <br />Computer Aided Analysis and Design, <br />System Hardware Design, <br />Physical Electronics, <br />Modern Electronic Design Techniques, <br />MOS Devices, <br />Special Semiconductor Devices, <br />Microelectronic Lab. <br /><br /><span style="font-size:130%;"><span style="font-weight: bold;">Projects at M.Tech</span>: </span><br />===================<br /> Study of Multi-layer Multi-chip Architecture. (Carried out at I. I. T.<br />Bombay during year 1998-2000) <br />Project consists of Design & development of IC interconnects of multi-layer<br />multi-chip architectures. The Elmore delay model is widely used in<br />optimizing the wire sizing area of interconnect. The wire sizing algorithms<br />such as Optimal Wire Sizing Algorithm under Elmore Delay, Greedy Wire<br />Sizing Algorithm under the Elmore Delay and Extended Optimal Wire Sizing<br />Algorithm under the Elmore Delay considered for the design of interconnects<br />in the circuit of multi-layer multi-chip architectures. The optimal wire<br />sizing solution satisfies a number of interesting properties such as<br />separability, monotone and dominance properties. These properties<br />considered while design of interconnects in the circuit. These algorithms<br />are implemented to get the fruitful results. The code is written in `C'<br />language. The results received are the delay required for the signal from<br />source node to the destination node (e.g. driver node to the sink node in<br />the circuit). The time complexity is calculated. User-friendly software<br />developed for complete analysis and design of interconnects in the circuit.<br /><br /><br />Languages:<br />==========<br />English, Hindi, Marathi.<br />Dutch, French (Beginner).<br /><br /><span style="font-weight: bold;">AREAS OF INTEREST: </span><br />==================<br />ASIC Design.<br />VLSI Design.<br />Process Technology.<br />ASIC / VLSI Verification & Testing.<br /><br />I am interested in relocating ANYWHERE in CANADA or<br />USA or EUROPE anywhere. I am confident that my<br />experience, abilities, skills and attitude to keep on<br />learning new things will help me prove the right<br />person for this job, and an asset to the team and your<br />company.Prakash Patilhttp://www.blogger.com/profile/16951218341664680207noreply@blogger.com0