ASIC Design Engineer

 

VLSI Design Engineer

Curriculum Vitae

================

Prakash Patil
E-mail
PraPatil@gmail.com
PraPatil2k@yahoo.com
Prakash.Patil.VLSI@Gmail.com
Semiconductor.Career@gmail.com
http://www.freewebs.com/prakashpatil

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Objective:
==========
To seek a challenging position in the field of VLSI / ASIC Design / Process
Technology / Test.

EXPERIENCE SUMMARY:
===================
One & half years of experience in physical design of Integrated Circuit
(IC) on 0.13 micron & 0.18 micron process. Good skills and experience of
deep sub micron IO pad library design, verification, and design of test
chip, ESD & LATCH-UP issues, and Failure analysis. Programming / Scripting
in SKILL, Perl, TCL, C. Good communication skills. Excellent leadership
qualities.

SKILLS OFFERED:
===============
ASIC / VLSI Physical Design, Process Technology, Test. Expert Currently
used 2 years.
Software Proficiency: Cadence Tool, Mentor Graphics calibre tool, Hspice /
Characterization techniques, ability to develop well-structured and
maintainable software tools.
Programming / scripting languages like SKILL, Perl and TCL, C, C++ etc.
O.S. platform: HP UNIX, Win NT, and LINUX.

Professional experience:
========================
3/2001 to 8/2002 Philips Semiconductors, The Netherlands.
Standard Cell Design Engineer.
Major role in Shrink CMOS18 micron & CMOS12 micron IO pad library
Design. Computer aided physical design of CMOS12 micron library design,
verification. Verification & merging of new cells to Standard cell library
& maintenance.
SHRINK CMOS18 library physical design, verification: Verification of new
cells, merging of new cells & maintenance of complete SHRINK CMOS18 IO pad
library. Complete SHRINK CMOS18 micron IO pad library converted from CMOS
18 IO pad library. All the IO pad layouts of SHRINK 18 micron standard cell
library converted from cmos18 library for SHRINK process. It itself is a
big project.
New Physical design Layout like level shifter, PCI, P1394, USB, PECL,
SSTL etc.
A role in the silicon qualification (electrical, ESD and Latch-up
issues) of the I/O libraries.
Design of test chips for IO pads of standard cell library and
participation in the testing and failure analysis.
Besides the general-purpose input, output and bi-directional cells, the
current libraries contain new cells developed according industrial
standards (SSTL-2, PCI, USB, PECL, etc.).
Well Versed with Physical Design aspects-Floor Planning, P & R, Clock
tree synthesis, links to DRC, LVS, etc. Familiarity with Mentor & Cadence
tools, Working knowledge of scripting languages like SKILL, PERL and TCL.
Ability to lead a team of engineers.

Software used: Cadence complete Backend Qualified Design flow (QDF
3.1), Skill scripts, and Calibre Mentor Graphics tool.
O.S. platform used: WinNT, HP-Unix.
Team Size: 4.

Training Undergone: Cadence Qualified Design flow (QDF 3.1): Three &
half day of extensive training on complete front end & backend design flow.
SKILL language: SKILL language for Cadence design tool. Extensive five days
of training.

Education:
==========
1998 - 03/2000 Indian Institute Of Technology Bombay, Mumbai, India
Master of Technology in Microelectronics with GPA 6.85 out of 10.
Some of the courses studied at M.Tech. are as:
VLSI Design,
VLSI Technology,
Computer Aided Analysis and Design,
System Hardware Design,
Physical Electronics,
Modern Electronic Design Techniques,
MOS Devices,
Special Semiconductor Devices,
Microelectronic Lab.

Projects at M.Tech:
===================
Study of Multi-layer Multi-chip Architecture. (Carried out at I. I. T.
Bombay during year 1998-2000)
Project consists of Design & development of IC interconnects of multi-layer
multi-chip architectures. The Elmore delay model is widely used in
optimizing the wire sizing area of interconnect. The wire sizing algorithms
such as Optimal Wire Sizing Algorithm under Elmore Delay, Greedy Wire
Sizing Algorithm under the Elmore Delay and Extended Optimal Wire Sizing
Algorithm under the Elmore Delay considered for the design of interconnects
in the circuit of multi-layer multi-chip architectures. The optimal wire
sizing solution satisfies a number of interesting properties such as
separability, monotone and dominance properties. These properties
considered while design of interconnects in the circuit. These algorithms
are implemented to get the fruitful results. The code is written in `C'
language. The results received are the delay required for the signal from
source node to the destination node (e.g. driver node to the sink node in
the circuit). The time complexity is calculated. User-friendly software
developed for complete analysis and design of interconnects in the circuit.


Languages:
==========
English, Hindi, Marathi.
Dutch, French (Beginner).

AREAS OF INTEREST:
==================
ASIC Design.
VLSI Design.
Process Technology.
ASIC / VLSI Verification & Testing.

I am interested in relocating ANYWHERE in CANADA or
USA or EUROPE anywhere. I am confident that my
experience, abilities, skills and attitude to keep on
learning new things will help me prove the right
person for this job, and an asset to the team and your
company.